Chip design for submicron VLSI :CMOS layout and simulation
Uyemura, John P.
Chip design for submicron VLSI :CMOS layout and simulation Uyemura, John P. - Cengage 2006
621.395 / T06 UYE
Chip design for submicron VLSI :CMOS layout and simulation Uyemura, John P. - Cengage 2006
621.395 / T06 UYE